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Integrated Circuit Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER
FEATURES
* 9 LVCMOS/LVTTL outputs * Selectable CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL * Maximum output frequency: 250MHz * Output skew: 115ps (maximum) * Part-to-part skew: 500ps (maximum) * Additive phase jitter, RMS: 0.02ps (typical) @ 3.3V * Full 3.3V or 2.5V operating supply * -40C to 85C ambient operating temperature * Pin compatible with the MPC947
GENERAL DESCRIPTION
The ICS83947I-147 is a low skew, 1-to-9 LVCMOS/LVTTL Fanout Buffer and a member of HiPerClockSTM the HiPerClockSTM family of High Performance Clock Solutions from ICS. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 9 to 18 by utilizing the ability of the outputs to drive two series terminated lines.
ICS
Guaranteed output and part-to-part skew characteristics make the ICS83947I-147 ideal for high performance, 3.3V or 2.5V single ended applications.
BLOCK DIAGRAM
CLK_EN D Q LE CLK0 CLK1 0
PIN ASSIGNMENT
GND GND GND VDDO VDDO Q0 Q1 Q2
32 31 30 29 28 27 26 25 Q0 GND CLK_SEL Q1 CLK0 CLK1 CLK_EN Q3 Q4 Q5 Q6 Q7 Q8 OE VDD GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GND VDDO Q8 GND Q7 VDDO Q6 GND
24 23 22
GND Q3 VDDO Q4 GND Q5 VDDO GND
1
CLK_SEL
Q2
ICS83947I-147
21 20 19 18 17
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
OE
83947AYI-147
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER
Name GND Type Power Input Input Input Input Power Pullup Description Power supply ground. Clock select input. When HIGH, selects CLK1. When LOW, selects CLK0. LVCMOS / LVTTL interface levels. Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 8, 9, 12, 16, 17, 20, 24, 25, 29, 32 2 3, 4 5 6 7
CLK_SEL CLK0, CLK1 CLK_EN OE VDD
Pullup Clock enable. LVCMOS / LVTTL interface levels. Pullup Output enable. LVCMOS / LVTTL interface levels. Core supply pin.
10, 14, 18, 22, 27, 31 VDDO Power Output supply pins. Q0 thru Q8 clock outputs. 11, 13, 15, 19, 21, Q8, Q7, Q6, Q5, Output 23, 26, 28, 30 Q4, Q3, Q2, Q1, Q0 LVCMOS / LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Output Impedance Test Conditions Minimum Typical 4 12 51 7 Maximum Units pF pF K
TABLE 3. OUTPUT ENABLE
Control Inputs OE 0 1 1 CLK_EN X 0 1
AND
CLOCK ENABLE FUNCTION TABLE
Output Q0:Q8 Hi-Z LOW Follows CLK input
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V0.3V OR 2.5V5%, TA = -40C TO 85C
Symbol Parameter VDD VDDO IDD IDDO Core Supply Voltage Output Supply Voltage Input Supply Current Output Supply Current Test Conditions Minimum 3.0 2.375 3.0 2.375 Typical 3.3 2.5 3.3 2.5 Maximum 3.6 2.625 3.6 2.625 50 9 Units V V V V mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V0.3V, TA = -40C TO 85C
Symbol Parameter VIH VIL IIN VOH Input High Voltage Input Low Voltage Input Current CLK0, CLK1, OE, CLK_SEL, CLK_EN IOH = -20mA -100 2.5 Test Conditions Minimum 2 Typical Maximum 3.6 0.8 Units V V A V
Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1 IOL = 20mA 0.4 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information Section, 3.3V Output Load Test Circuit Diagram.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol Parameter VIH VIL IIH IIL VOH Input High Voltage Input Low Voltage Input High Current Input Low Current CLK0, CLK1 CLK_SEL, CLK_EN, OE CLK0, CLK1, OE, CLK_SEL, CLK_EN CLK0, CLK1, OE, CLK_SEL, CLK_EN VDD = VIN = 2.625V VDD = 32.625V, VIN = 0V -150 1.8 Test Conditions Minimum 2 -0.3 -0.3 Typical Maximum VDD + 0.3 1.3 0.8 5 Units V V V A A V
Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information Section, 2.5V Output Load Test Circuit Diagram.
83947AYI-147
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER
Test Conditions f 250MHZ Measured on rising edge @VDDO/2 Measured on rising edge @VDDO/2 (12KHz to 20MHz) 0.8V to 2.0V f > 133MHz f 133MHz 0.2 tPeriod/2 - 1 40 Minimum 2 Typical Maximum 250 4.2 115 500 Units MHz ns ps ps ps 1 tPeriod/2 + 1 60 10 10 0 ns ns % ns ns ns
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V0.3V, TA = -40C TO 85C
Symbol Parameter fMAX Output Frequency tPD Propagation Delay, NOTE 1 Output Skew; NOTE 2, 5 Par t-to-Par t Skew; NOTE 3, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Output Pulse Width Output Duty Cycle Output Enable Time; NOTE 4 Output Disable Time; NOTE 4 Clock Enable Setup Time
tsk(o) tsk(pp)
tjit(O) t R / tF tPW odc tEN tDIS tS
0.2
Clock Enable Hold Time 1 ns tS All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = -40C TO 85C
Symbol Parameter fMAX Output Frequency tPD Propagation Delay, NOTE 1 Output Skew; NOTE 2, 5 Par t-to-Par t Skew; NOTE 3, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Output Pulse Width Output Enable Time; NOTE 4 Output Disable Time; NOTE 4 Clock Enable Setup Time 0 Test Conditions f 250MHZ Measured on rising edge @VDDO/2 Measured on rising edge @VDDO/2 (12KHz to 20MHz) 20% - 80% 300 tPeriod/2 - 1.2 Minimum 2.4 Typical Maximum 250 4.5 130 600 0.1 800 tPeriod/2 + 1.2 10 10 Units MHz ns ps ps ps ps ns ns ns ns
tsk(o) tsk(pp) tjit(O)
tR / tF tPW t EN tDIS tS
Clock Enable Hold Time 1 ns tS All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
83947AYI-147
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz) = 0.02ps typical @ 3.3V
SSB PHASE NOISE dBc/HZ
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k
Additive Phase Jitter, RMS @
156.25MHz (12KHz to 20MHz) = 0.01ps typical @ 2.5V
SSB PHASE NOISE dBc/HZ
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de83947AYI-147
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
REV. A SEPTEMBER 24, 2004
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Integrated Circuit Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 0.15V 1.25V5%
VDD, VDDO
Qx
SCOPE
VDD, VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V 0.15V
-1.25V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
PART 1 Qx
V
DDO
V
DDO
2
Qx
2
PART 2 Qy
V
DDO
V
DDO
2 tsk(pp)
Qy
2 tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
VDDO 2 t PW t PERIOD
CLK0,CLK1
VDD 2
VDDO Q0:Q8 2
VDDO 2
Q0:Q8
VDDO 2 t
PD
odc =
t PW t PERIOD
PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
2V 0.8V tR
2V 0.8V tF 20%
80%
80% 20%
Clock Outputs
Clock Outputs
tR
tF
3.3V OUTPUT RISE/FALL TIME
83947AYI-147
2.5V OUTPUT RISE/FALL TIME
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER
For the LVCMOS output drivers, only one termination example is shown in this schematic. Additional termination approaches are shown in the LVCMOS Termination Application Note (refer to ICS website).
APPLICATION SCHEMATIC EXAMPLE
Figure 1 shows an example of ICS83947I-147 application schematic. In this example, the device is operated at VCC=3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVCMOS driver.
VDDO
R1
43
Zo = 50
VCC
R3
43
Zo = 50 Ohm
32 31 30 29 28 27 26 25
U1 ICS83947I-147
LVCMOS
1 2 3 4 5 6 7 8
GND VDDO Q0 GND Q1 VDDO Q2 GND
VCC
R3
43
Zo = 50 Ohm
GND CLK_SEL CLK0 CLK1 CLK_EN OE VDD GND
GND VDDO Q8 GND Q7 VDDO Q6 GND
GND Q3 VDDO Q4 GND Q5 VDDO GND
24 23 22 21 20 19 18 17
VDD
LVCMOS
C5 0.1u
VDD=3.3V
VDDO=3.3V
VDDO
(U1-10)
(U1-14)
(U1-18)
(U1-22)
(U1-27)
(U1-31)
R2 43
9 10 11 12 13 14 15 16
Zo = 50
C1 0.1u
C2 0.1u
C3 0.1u
C4 0.1u
C2 0.1u
C3 0.1u
FIGURE 1. ICS83947I-147 SCHEMATIC LAYOUT
83947AYI-147
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83947I-147 is: 1040
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REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER
32 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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9
REV. A SEPTEMBER 24, 2004
Integrated Circuit Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER
Marking ICS83947AI147 ICS83947AI147 Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS83947AYI-147 ICS83947AYI-147T
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83947AYI-147
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REV. A SEPTEMBER 24, 2004

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